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MC100EP016A 3.3 V ECL 8-Bit Synchronous Binary Up Counter
Description
The MC100EP016A is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the ECLinPSTM family MC100E016 with higher operating speed. The counter features internal feedback to TC gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. COUT and COUT provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUT should not be used in cascade configuration. Only TC should be used for a counter or divider cascade chain output. A differential clock input has also been added to improve performance. The 100 Series contains temperature compensation.
Features
http://onsemi.com MARKING DIAGRAM*
MC100 EP016A AWLYYWWG LQFP-32 FA SUFFIX CASE 873A A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
* 550 ps Typical Propagation Delay * Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016 * PECL Mode Operating Range: VCC = 3.0 V to 3.6 V * NECL Mode Operating Range: VCC = 0 V * * * * * * * * * *
with VEE = 0 V with VEE = -3.0 V to -3.6 V Open Input Default State Safety Clamp on Clock Inputs Internal TC Feedback (Gated) Addition of COUT and COUT 8-Bit Differential Clock Input VBB Output Fully Synchronous Counting and TC Generation Asynchronous Master Reset Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November 2006 - Rev. 6
1
Publication Order Number: MC100EP016A/D
MC100EP016A
VBB CLK CLK P0 P1 P2 P3 P4
24 PE CE MR VEE Q0 Q1 Q2 VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 P5 P6 P7 VCC TC COUT
Table 1. PIN DESCRIPTION
PIN P0-P7* Q0-Q7 CE* PE* MR* CLK*, CLK* TC FUNCTION ECL Parallel Data (Preset) Inputs ECL Data Outputs ECL Count Enable Control Input ECL Parallel Load Enable Control Input ECL Master Reset ECL Differential Clock ECL Terminal Count Output ECL TC-Load Control Input ECL Differential Output Positive Supply Negative Supply Reference Voltage Output
MC100EP016A
13 12 11 10 9
TCLD* COUT COUT, COUT VEE VCC VEE VBB
2
3
4
5
6
7
8
* Pins will default LOW when left open. VCC Q3 Q4 Q5 Q6 Q7 TCLD VCC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View) Table 2. FUNCTION TABLES
CE X L L H X X PE L H H H X X TCLD MR X L H X X X L L L L L H CLK Z Z Z Z ZZ X FUNCTION Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC = LOW Hold Masters Respond, Slaves Hold Reset (Qn : = LOW, TC : = HIGH)
ZZ = Clock Pulse (High-to-Low) Z = Clock Pulse (Low-to-High)
Table 3. FUNCTION TABLE
Function Load Count PE L H H H H L H H H H H H H H X CE X L L L L X H H L L L L L L X MR L L L L L L L L L L L L L L H TCLD X L L L L X X X H H H H H H X CLK Z Z Z Z Z Z Z Z Z Z Z Z Z Z X P7-P4 H X X X X H X X H H H H H H X P3 H X X X X H X X L L L L L L X P2 H X X X X H X X H H H H H H X P1 L X X X X L X X H H H H H H X P0 L X X X X L X X L L L L L L X Q7-Q4 H H H H L H H H H H H H H H L Q3 H H H H L H H H H H H L L H L Q2 H H H H L H H H H H H H H L L Q1 L L H H L L L L L H H H H L L Q0 L H L H L L L L H L H L H L L TC H H H L H H H H H H L H H H H COUT H H H L H H H H H H L H H H H COUT L L L H L L L L L L H L L L L
Load Hold
Load on Terminal Count
Reset
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MC100EP016A
Q0 PE TCLD Q1 Q7
Q0M CE BIT 0 P0 P1 MASTER Q0M SLAVE Q0 CE BIT 1
CE Q Q1 0 Q2 Q3 Q Q5 Q4
6
BIT 7
P7
MR CLK CLK
BITS 2-6
TC
5
VBB VEE
COUT COUT
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
Figure 2. 8-BIT Binary Counter Logic Diagram
Table 4. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 Value 75 kW N/A > 2 kV > 100 V > 2 kV Pb-Free Pkg Level 2
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
UL 94 V-0 @ 0.125 in 1226 Devices
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MC100EP016A
Table 5. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 32 LQFP 32 LQFP 32 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +70 -65 to +150 74 61 12 to 17 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100EP016A
Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 130 2155 1355 2075 1355 1775 2.0 1875 Typ 170 2280 1480 Max 210 2405 1605 2420 1675 1975 3.3 Min 130 2155 1355 2075 1355 1775 2.0 1875 25C Typ 177 2280 1480 Max 210 2405 1605 2420 1675 1975 3.3 Min 130 2155 1355 2075 1355 1775 2.0 1875 70C Typ 180 2280 1480 Max 210 2405 1605 2420 1675 1975 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 3. All loading with 50 ohms to VCC-2.0 volts. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.6 V to -3.0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output LOW Voltage (Note 6) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) Input HIGH Current Input LOW Current 0.5 Min 130 -1145 -1945 -1225 -1945 -1525 -1425 Typ 170 -1020 -1820 Max 210 -895 -1695 -880 -1625 -1325 0.0 Min 130 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 177 -1020 -1820 Max 210 -895 -1695 -880 -1625 -1325 0.0 Min 130 -1145 -1945 -1225 -1945 -1525 -1425 70C Typ 180 -1020 -1820 Max 210 -895 -1695 -880 -1625 -1325 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. All loading with 50 ohms to VCC-2.0 volts. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP016A
Table 8. AC CHARACTERISTICS VEE = -3.0 V to -3.6 V; VCC = 0 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 8)
-40C Symbol fCOUNT Characteristic Maximum Frequency Count & Division Modes Q, TC, COUT/COUT Propagation Delay CLK to Q MR to Q CLK to TC MR to TC CLK to COUT/COUT MR to COUT/COUT P0 P1 to P4 P5 to P7 CE PE TCLD P0 P1 to P4 P5 to P7 CE PE TCLD Min 1.3 350 400 350 400 475 450 400 300 250 500 500 550 100 50 150 600 625 525 Typ 1.5 511 550 511 555 705 720 240 140 80 320 315 355 -145 -160 -105 380 465 320 2.6 400 550 550 90 195 365 380 180 320 8.5 400 550 550 100 650 700 650 700 850 850 Max Min 1.2 400 400 400 400 500 500 400 300 250 500 500 550 100 50 150 600 625 525 25C Typ 1.4 550 570 550 570 745 760 240 135 65 330 320 365 -155 -170 -110 410 500 325 2.5 205 365 380 190 320 8.0 400 550 550 125 700 750 700 750 900 900 Max Min 1.2 480 450 480 520 550 570 400 300 250 500 500 550 100 50 150 600 625 525 70C Typ 1.3 610 630 610 635 825 830 245 125 55 340 325 380 -170 -180 -115 450 535 340 2.5 220 370 380 215 450 8.0 780 820 780 820 1000 950 ps Max Unit GHz
tPLH tPHL
tS
Setup Time
ps
tH
Hold Time
ps
tJITTER tRR tPW tr, tf
Clock Random Jitter (RMS, 1000 Waveforms) Reset Recovery Time Minimum Pulse Width CLK Minimum Pulse Width MR Output Rise/Fall Times 20% - 80%
ps ps ps ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to VCC-2.0 V.
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MC100EP016A
Applications Information Cascading Multiple EP016A Devices For applications which call for larger than 8-bit counters multiple EP016As can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of EP016A devices. Two EP016As can be cascaded without the need for external gating, however for counters wider than 16 bits external OR gates are necessary for cascade implementations. Figure 3 below pictorially illustrates the cascading of 4 EP016As to build a 32-bit high frequency counter. Note the EP01 gates used to OR the terminal count outputs of the lower order EP016As to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant EP016A is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an EP016A in the chain to count, all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting EP016A devices from Figure 3 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for a cascaded counter chain is set by the propagation delay of the TC output, the necessary setup time of the CE input, and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC propagation delay and the CE setup time). Figure 3 shows EP01 gates used to control the count enable inputs, however, if the frequency of operation is slow enough, a LVECL OR gate can be used. Using the worst case guarantees for these parameters.
LOAD Q0 to Q7 LO CE PE EP016 LSB CLK CLK TC Q0 to Q7 CE PE EP016 Q0 to Q7 CE PE EP016 Q0 to Q7 CE PE
EP016 MSB CLK CLK
EP01
CLK CLK
TC
EP01
CLK CLK
TC
TC
P0 to P7 CLK CLK
P0 to P7
P0 to P7
P0 to P7
Figure 3. 32-Bit Cascaded EP016A Counter
Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case estimates of these delays need to be added to the calculations.
Programmable Divider
The EP016A has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn's) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 4 below illustrates the input conditions necessary for utilizing the EP016A as a programmable divider set up to divide by 113.
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MC100EP016A
Applications Information (continued)
H L L L P4 H P3 H H H
Table 9. Preset Values for Various Divide Ratios
Divide Ratio TC 2 3 4 5 * P7 H H H H * * H H H * * L L L P6 H H H H * * L L L * * L L L Preset Data Inputs P5 H H H H * * L L L * * L L L P4 H H H H * * H L L * * L L L P3 H H H H * * L H H * * L L L P2 H H H L * * L H H * * L L L P1 H L L H * * L H H * * H L L P0 L H L H * * L H L * * L H L
P7 P6 P5 H L H PE CE TCLD CLK CLK Q7 Q6 Q5
P2 P1 P0
COUT COUT Q4 Q3 Q2 Q1 Q0
Figure 4. Mod 2 to 256 Programmable Divider
* 112 113 114 * * 254 255 256
To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. As an example for a divide ratio of 113: Pn's = 256 - 113 = 8F16 = 1000 1111 where: P0 = LSB and P7 = MSB Forcing this input condition as per the setup in Figure 4 will result in the waveforms of Figure 5. Note that the TC output is used as the divide output and the pulse duration is equal to a full clock period. For even divide ratios, twice the desired divide ratio can be loaded into the EP016A and the TC output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle.
A single EP016A can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed multiple EP016As can be cascaded in a manner similar to that already discussed. When EP016As are cascaded to build larger dividers the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC pins must be used for multiple EP016A divider chains.
Load CLK
1001 0000
1001 0001 1111 1100 ***
1111 1101
1111 1110
1111 1111
Load
*** PE *** TC DIVIDE BY 113
Figure 5. Divide by 113 EP016A Programmable Divider Waveforms
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MC100EP016A
Applications Information (continued)
EP01
Q0 to Q7 LO CE EP016 LSB CLK CLK TC PE
Q0 to Q7 CE PE EP016
Q0 to Q7 CE EP016 PE
Q0 to Q7 CE EP016 MSB CLK CLK
EP01
PE
CLK CLK
TC
EP01
CLK CLK
TC
TC
P0 to P7
P0 to P7
P0 to P7
P0 to P7
CLK CLK
Figure 6. 32-Bit Cascaded EP016A Programmable Divider
Figure 6 shows a typical block diagram of a 32-bit divider chain. Once again to maximize the frequency of operation EP01 OR gates were used. For lower frequency applications a slower OR gate could replace the EP01. Note that for a 16-bit divider the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant EP016A must also feed the CE input of the most significant EP016A. If the two TC outputs were OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device.
Maximizing EP016A Count Frequency
The EP016A device produces 9 fast transitioning single ended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100EP016A
ORDERING INFORMATION
Device MC100EP016AFA MC100EP016AFAG MC100EP016AFAR2 MC100EP016AFAR2G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EP016A
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
32
A1
A
25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V V1
AE P AE
17
DETAIL Y
BASE METAL
N 9 -Z- S
8X M_
S1
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD K Q_
GAUGE PLANE
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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MC100EP016A/D
0.20 (0.008)
0.20 (0.008) AC T-U Z
F
EE EE EE
9
D
M
4X
AC T-U Z
DETAIL Y
-T-, -U-, -Z-

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